AutoDMA Transfers
Receiver DMA
address, the address increment, the number of transfers, and the control
bits.
Once setup is complete, when an external master (either a host or another
TigerSHARC) writes to the AutoDMA register, a DMA request is initi-
ated and the DMA channels transfers the data to the internal memory.
Link Transfers
Link DMA transfers handle data transmitted and received through the
TigerSHARC processor's link ports. The following features are included.
• External/internal memory to link port transfers
Transmitter DMA
nal/internal memory address, the address increment, the number of
transfers, and the control bits.
Once transmitter
start automatically and continue until the block transfer is com-
pleted. The transmitting link port generates a DMA request if it is
ready to receive data for transmission. The DMA from exter-
nal/internal memory to the link port is then completed. This
process is repeated until the entire data block is transferred.
• Link port to external/internal memory transfers
Receiver DMA
nal/internal memory address, the address increment, the number of
transfers, and the control bits.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
registers are programmed with the internal memory
TCB
registers are programmed with the exter-
TCB
programming is complete, DMA transfers
TCB
registers are programmed with the exter-
TCB
Direct Memory Access
7-9
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