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4 INTERRUPTS
The TigerSHARC processor supports several types of interrupts— inter-
nal and external interrupts can serve any of the following purposes.
• For synchronization between core and non-core operations
• For error detection
• For using debug features
• For introducing control by an application
Most interrupts in the TigerSHARC processor are dedicated. Four inter-
rupt pins and one interrupt register support general-purpose interrupts.
All interrupt sources other than the interrupt pins and interrupt register
are caused by events or dedicated hardware. For each interrupt there is a
vector register in the Interrupt Vector Table (IVT) (in register groups
0x38 and 0x39) and a bit number in the interrupt flags and mask registers.
For performance considerations, when a hardware interrupt occurs, it does
not break the pipeline. The first instruction of the interrupt routine is
inserted into the instruction flow after it has occurred. From this point,
the instructions that are already in the pipeline complete their execution.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
4-1
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