Dma Interrupts - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Controller Operations

DMA Interrupts

An interrupt is generated by the DMA if the
is set (see "DPx Register" on page 7-18) and when the count register (the
X count field in
zero and the last transaction is completed. The count register(s) must dec-
rement to zero as a result of the actual DMA transfers—merely writing
zero to a count register does not generate the interrupt.
Each DMA channel
latched in the
ILAT
information, see "DMA Interrupts" on page 4-5.
!
Although the EP DMA channel access priority rotates, the inter-
rupt priorities of all DMA channels are fixed.
As an alternative to interrupts, polling the
determine when a single DMA sequence has completed. If chaining is
enabled, however, polling the
DMA sequence may be underway by the time the polled status is returned.
Starting and Stopping DMA Sequences
This section discusses starting, ending, suspending, and resuming DMA
sequences.
Starting a DMA Sequence
A DMA sequence starts when one of the following occurs:
• The DMA channel is enabled, chaining is disabled, the DMA
request bit is set, and a DMA request input transitions from high
to low.
• The DMA channel is enabled, chaining is disabled, and the DMA
request bit is cleared.
7-48
register ) of an active DMA channel decrements to
CB DX
has its own interrupt. The DMA interrupts are
TCB
register and are enabled in the
DSTAT
bit in the
INT
IMASK
register can be used to
DSTAT
should not be used because the next
ADSP-TS101 TigerSHARC Processor
Hardware Reference
register
TCBx DP
register. For more