Multiprocessor Host Booting - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Booting

Multiprocessor Host Booting

If the pin is sampled high during reset, this causes the processor to go
BMS
into idle and disables master mode boot DMA. When the processor is in
idle state waiting for a host or link boot, any signal from the host or link
causes a slave mode boot.
• A host can boot each processor using the pipelined protocol and
and
HBR
• Any TigerSHARC processor that was already booted via an
EPROM, host or link Port can boot others through the external
port.
Host booting multiple processors requires that the host monitor the status
of the AutoDMA via the DMA status register
of the AutoDMA buffer does not occur during the boot process. Buffer
overrun can occur when the boot loader kernel executes time-consuming
memory initializations which delay servicing of the host writes to the
AutoDMA buffer.
Recommended process for booting multiple processors via a host:
1. As described in Engineer-to-Engineer Note EE-174: ADSP-TS101
Boot Loader Kernels Operation, disable the active AutoDMA
every processor, reconfigure the
fers in every processor, re-enable the
proceed with host boot using normal-word transfers during the
entire boot process.
2. Host performs MMS Broadcast writes to the AutoDMA channel 0
of all processors in multiprocessor system. (Recall: Writes to the
broadcast region access the internal memory of all processors in the
multiprocessing system. For more information on MMS space and
broadcast writes, "Internal Memory Access" on page 2-7).
10-30
.
HBG
to ensure that overrun
DSTAT
to perform normal-word trans-
TCB
in every processor and
TCB
ADSP-TS101 TigerSHARC Processor
Hardware Reference
in
TCB