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The IALUs also support bit-reverse addressing, which is useful for the Fast
Fourier Transform FFT algorithm. Bit-reverse addressing is implemented
using a reverse carry addition that is similar to regular additions, but the
carry is taken from the upper bits and is driven into lower bits.
The IALU provides flexibility in moving data as single, dual, or quad-
words. Every instruction can execute with a throughput of one per cycle.
IALU instructions execute with a single cycle of latency while computa-
tion units have two cycles of latency. Normally, there are no dependency
delays between IALU instructions, but if there are, three or four cycles of
latency can occur.
For more information on the IALUs, see "IALU Registers" on page 2-14.
Program Sequencer
The program sequencer supplies instruction addresses to memory and,
together with the IALUs, allows computational operations to execute with
maximum efficiency. The sequencer supports efficient branching using
the branch target buffer (BTB), which reduces branch delays for condi-
tional and unconditional instructions.
The TigerSHARC processor achieves its fast execution rate by means of an
eight-cycle pipeline.
Two stages of the sequencer's pipeline actually execute in the computation
units. The computation units perform single-cycle operations with a two-
cycle computation pipeline, meaning that results are available for use two
cycles after the operation is begun. Hardware causes a stall if a result is not
available in a given cycle (register dependency check). Up to two compu-
tation instructions per compute block can be issued in each cycle,
instructing the ALU, multiplier, or shifter to perform independent, simul-
taneous operations.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Introduction
1-13
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