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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1
1 1 0 0 1 1 1 1 0 0 1 1 1
Bit 16 continued on Figure 2-10
Figure 2-11. SYSCON (Lower) Register Bit Descriptions
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Memory and Register Map
BANK 0 IDLE BIT
Same definitions as Host bits.
BANK 0 INTERVAL WAIT BITS
Same definitions as Host bits.
BANK 0 PIPE DEPTH BITS
Same definitions as Host bits.
BANK 0 SLOW PROTOCOL BIT
Same definitions as Host bits.
BANK 1 IDLE BIT
Same definitions as Host bits.
BANK 1 INTERVAL WAIT BITS
Same definitions as Host bits.
BANK 1 PIPE DEPTH BITS
Same definitions as Host bits.
BANK 1 SLOW PROTOCOL BIT
Same definitions as Host bits.
HOST IDLE BIT
1 – Idle cycle inserted between transac-
tions from this bank.
0 – No idle cycle inserted.
HOST INTERVAL WAIT BITS
00 – Zero wait cycle
01 – One wait cycle
10 – Two wait cycles
11 – Three wait cycles
HOST PIPE DEPTH BITS
2-35
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