Host Boot - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Booting
Analog Devices supplies a default EPROM boot loader kernel
(
TS101_prom.asm
ADSP-TS101
Figure 10-4. PROM Booting

Host Boot

Booting the TigerSHARC processor from a 32-bit or 64-bit host processor
is performed via the data and address buses of the external port.
The pin is used as the strap option for the selection. If the
BMS
sampled high during reset, this causes the processor to go into idle and
disables master mode boot DMA. When the processor is in idle state wait-
ing for a host or link boot, any signal from the host or link causes a slave
mode boot.
Host boot uses the TigerSHARC processor AutoDMA channels. Either
AutoDMA channel can be used since both AutoDMA channels
(AUTODMA0 and AUTODMA1) are active and initialized at reset to
transfer 256 words of code and/or data into the TigerSHARC processor's
internal memory block 0, locations 0x00-0xff. The corresponding DMA
interrupt vectors are initialized to 0. An interrupt occurs at the completion
of the DMA transfer and the TigerSHARC processor starts executing the
boot loader kernel at internal memory location 0x0. It is intended that
these first 256 words act as a boot loader to initialize the rest of Tiger-
SHARC processor internal memory. The boot loader kernel then brings in
the application code and data through a series of single-word DMA trans-
fers. Finally, the boot loader kernel overwrites itself with the application
10-22
).
ADDRESS
A23-0
D7-0
8-BIT DATA
BMS
RD
A23-0
D1-0
ADSP-TS101 TigerSHARC Processor
Hardware Reference
8-BIT EPROM
CS OE
pin is
BMS