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Table 10-2. General Pin Descriptions (Cont'd)
Signal
IOEN
IRQ3–0
LxCLKIN
LxCLKOUT
LxDAT7–0
LxDIR
LCLK_N
LCLK_P
LCLKRAT2–0
LDQM
MS1–0
MSH
MSSD
NC
RAS
RD
RESET
SCLK_N
SCLK_P
SCLKFREQ
SDA10
SDCKE
SDWE
TCK
10-6
Type
Description
O/T
I/O Device Output Enable
I/A
Interrupt Request
I/A
Linkx Clock/Acknowledge Input
O
Linkx Clock/Acknowledge Output
I/O
Linkx Data 7–0
O
Link0 Direction. (0 = input, 1 = output)
Local Clock Reference
I
Local Clock Input, DSP clock input
I
LCLK Ratio
O/T
Low Word SDRAM Data Mask
O/T
Memory Select
O/T
Memory Select Host
I/O/T
Memory Select SDRAM
No Connect
I/O/T
Row Address Select
I/O/T
Memory Read
I/A
Reset
I
System Clock Reference
I
System Clock Input
I
SCLK Frequency
O/T
SDRAM Address bit 10 pin
I/O/T
SDRAM Clock Enable
I/O/T
SDRAM Write Enable
I
Test Clock (JTAG)
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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