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Debug Resources
When the control register is set to a non-idle operation, the count field is
set to the initial count. After the count field is reset, the watchpoint hard-
ware monitors the internal buses for:
• Transaction addresses matching what is specified in the watchpoint
address registers.
• The identity of the master that had initiated a transaction when it
matches one of those indicated by the control register.
Whenever there is a match, the counter is decremented.
After the counter reaches zero, an exception is initiated—either a supervi-
sor exception or an emulator trap according to Bit11–10 in the
field in
WPiCTL
count expired'. To begin another search, the user must rewrite the control
register.
Watchpoint Status (WPiSTAT)
The
register indicates the current status of the search. It holds the
WPiSTAT
current count of the search and the mode the watchpoint is executing.
When the counter expires, the watchpoint status Bits17–16 change to 11.
Reserved
Figure 9-3. WPxSTAT (Upper) Register Bit Descriptions
9-8
. At this point, the Status register indicates 'watchpoint
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EX Execution
0 0 0 0 0 0 0 0 0 0 0 0
ADSP-TS101 TigerSHARC Processor
EXtype
0 0 0 0
Hardware Reference
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