Table of Contents
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INDEX
AutoDMA Register Control 7-33
AutoDMA Register 2-44
AutoDMA Registers 2-43
AutoDMA Transfers 7-9
AutoDMA0 Register 2-44
AutoDMA1Register 2-44
B
Back Off (BOFF) 2-4, 5-39, 5-50–
5-51
Backoff 5-50
Bank Active (ACT) Command
6-33
Basic Transaction 5-16
BFOTMP register 1-11
bit
operations 1-11
Bit Wise Barrel Shifter (Shifter)
1-11
bit wise barrel shifter, See shifter
bit-reversed addressing 1-13
BMAX Current Value 2-39
BMAX maximum cycle count
2-39, 2-41, 5-41, 5-47
BMAX Register 2-39
BMAX Register Bit Descriptions
2-40, 2-41
boot 3-1, 4-2, 4-6, 10-32
boot by another master 3-1
EPROM boot (BMS) 3-1, 4-2,
5-5, 10-8, 10-32–10-34
link boot 3-1, 4-2, 8-7
no boot 3-1
Boot AutoDMA Register to Inter-
ii
nal Memory 10-37
Boot EPROM to Internal Memory
10-33
Boot Link to Internal Memory
10-36
Boot Memory Select (BMS) 5-5,
5-32
boot memory select (BMS) 10-8
Booting 1-24, 10-18
booting 1-18, 1-24, 10-18
EPROM 10-20
flash device 10-20
general scenario 10-19
link port 10-24
software development tools
support for 10-18
Booting a Multiprocessor System
10-26
Booting a Single ADSP-TS101S
10-20
branch
prediction 1-14, 4-10
branch target buffer 1-7, 1-13, 1-14
Branch Target Buffer (BTB) 2-10,
3-4
broadcast 2-6, 2-11, 2-12, 4-8, 4-9
Broadcast Distribution 2-7, 2-8
Broadcast Transfer 2-11
Broadcast Write 2-7, 2-8
Bstop (Burst stop command) 6-34,
6-35, 6-38, 6-39
Burst (BRST) 5-5, 5-16, 5-18, 5-50
bus 1-16
bus arbitration 1-20, 5-1, 5-3, 5-5,
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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