Tigersharc Processor Pins - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

TigerSHARC Processor Pins

This section describes the pins of the TigerSHARC processor and shows
how these signals can be used in your system. Figure 10-1 illustrates how
the pins are used in a single processor system.
Figure 10-1. Basic TigerSHARC Processor System
ADSP-TS101 TigerSHARC Processor
Hardware Reference
ADSP-TS101
LCLK_P
CLOCK
SCLK_P
S/LCLK_N
V
REFERENCE
REF
LCLKRAT2–0
SCLKFREQ
IRQ3–0
FLAG3–0
SDRAM
ID2–0
MEMORY
(OPTIONAL)
CS
CLK MSSD
ADDR
RAS
RAS
CAS
DATA
CAS
LDQM
DQM
HDQM
WE
SDWE
CKE
SDCKE
A10
SDA10
FLYBY
IOEN
LXDAT7–0
LINK
DEVICES LXCLKIN
(4 MAX)
LXCLKOUT
(OPTIONAL)
LXDIR
TMR0E
BM
BUSLOCK
CONTROLIMP2–0
DS2–0
RESET
BMS
BRST
ADDR31–0
DATA63–0
RD
WRH/WRL
ACK
MS1–0
MSH
HBR
HBG
BR7–1
CPA
DPA
BOFF
DMAR3–0
JTAG
System Design
BOOT
EPROM
(OPTIONAL)
CS
ADDR
DATA
MEMORY
(OPTIONAL)
ADDR
DATA
OE
WE
ACK
CS
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
DMA DEVICE
(OPTIONAL)
DATA
10-3