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Multiprocessing
All on-chip arbiters in a cluster of TigerSHARC processors operate in
lock-step on a cycle-by-cycle basis. In this way, every TigerSHARC pro-
cessor tracks and follows the arbitration sequence of the shared bus. Bus
arbitration is accomplished with the use of the
The
pins arbitrate between TigerSHARC processors, and
BR7-0
pins pass control of the bus to the host. If the system has less than
HBG
eight TigerSHARC processors, any unused
Every TigerSHARC processor has three identification input pins used to
distinguish between TigerSHARC processors. These are the
where the
ID2-0
number and used as the processor ID. A rotating bus priority is imple-
mented to ensure bus fairness between TigerSHARC processors. After
reset, the TigerSHARC processor with ID=000 becomes the master and
priority rotates in a round robin fashion, going up from the present mas-
ter. Priority rotation is interrupted either when the host that has highest
priority in the system requests the bus, or when a TigerSHARC processor
requests the bus by activating the
!
In previous SHARC processors (ADSP-2106x and ADSP-2116x
families), the use of a processor with ID=001 was mandatory for
multiprocessing systems to function correctly. The SHARC proces-
sors use ID=001 to select the bus master after reset and reserve
ID=000 for single processor systems.
In TigerSHARC processors, the ID pins operate differently. Multi-
processing TigerSHARC systems must always have a processor
with ID=000, which is the bus master after reset. Under some cir-
cumstances, multiprocessing TigerSHARC systems cannot
function properly unless a processor with ID=000 is present. For
example, the ID=000 processor must be present in any system
including SDRAM because this processor performs the initializa-
tion (Mode Register Set
related to open drain pull-ups which are only enabled on the pro-
cessor with ID=000.
5-40
pins of each TigerSHARC processor are set to a unique
CPA
MRS
,
BR7-0
pins must be deasserted.
BRx
and
(Priority Access) pins.
DPA
) of the SDRAM. Also, there are issues
ADSP-TS101 TigerSHARC Processor
and
pins.
HBR
HBG
and
HBR
pins,
ID2-0
Hardware Reference
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