Interrupt Service - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Interrupt Service

Example
During normal operations the
0xFF...F.
1. Assume that a link #0 interrupt occurred.
PMASK
rupts of lower priority than link #0—namely, timer low
priority interrupts and link #0 interrupt—are disabled by
PMASK
2. Following this, assume a DMA #2 interrupt occurred.
PMASK
timer low priority, link, and DMA #0, #1 and #2 interrupts
are disabled by
DMA #2 interrupt) clears the most significant set bit in
PMASK
0x00...040, and
ority interrupts and link #0 interrupt are disabled by
but the other link interrupts and DMA interrupts are
enabled again.
Interrupt Service
When an interrupt occurs, the corresponding bit in the
The bits are AND'ed with the enable bits in the
ILAT
. If the global interrupt enable bit is set and the result of the
PMASK_R
and and
IMASK
enabled is served.
4-14
= 0x00...040, and
.
= 0x00....08040, and
PMASK
which is bit #15.
PMASK_R
is not zero, the highest priority interrupt that is
PMASK_R
is zero, and
PMASK
= 0xFF...F80. The inter-
PMASK_R
is 0xFF...F0000. The
PMASK_R
. Returning from interrupt (which is
register is now
The PMASK
is 0xFF...F80. The timer low pri-
ADSP-TS101 TigerSHARC Processor
is
PMASK_R
PMASK
register is set.
ILAT
and with
IMASK
ILAT
Hardware Reference
,