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address connection is according to the bus width and there is an option to
split the load on different pins. For 32-bit bus, the connection is listed
below.
• SDRAM address Bits9–0 are connected to TigerSHARC processor
ADDR9–0
• SDRAM address Bit10 is connected to TigerSHARC processor pin
SDA10
• SDRAM address Bits15–11 are connected to TigerSHARC proces-
sor
ADDR15–11
In a 64-bit bus, the address should be shifted. The scheme should be as
follows.
• SDRAM address Bits9–0 are connected to TigerSHARC processor
ADDR10–1
• SDRAM address Bit10 is connected to TigerSHARC processor pin
SDA10
• SDRAM address Bits14–11 are connected to TigerSHARC proces-
sor
ADDR15–12
The control signals are specific SDRAM control signals. These signals are
listed below.
•
– SDRAM Chip Select
MSSD
•
– Row Address Strobe
RAS
•
– Column Address Strobe
CAS
•
– SDRAM Write Enable
SDWE
•
– Data Mask for Low Word (data Bits31–0)
LDQM
ADSP-TS101 TigerSHARC Processor
Hardware Reference
(or as many as required)
(or as many as required)
SDRAM Interface
6-9
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