Memory And Register Map; Memory Access Features - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

2 MEMORY AND REGISTER
MAP
This chapter describes the TigerSHARC processor memory and register
map. For information on using registers for computations and memory for
register loads and stores, see the ADSP-TS101 TigerSHARC Processor Pro-
gramming Reference. For information on using registers for configuring the
TigerSHARC processor's peripherals use the applicable chapters in this
book.

Memory Access Features

The TigerSHARC processor has three internal memory blocks M0, M1,
and M2 as shown in the system block diagram on Figure 1-2 on page 1-3.
Each memory block consists of 2M bits of memory space, and is config-
ured as 64k words each 32-bits in width. There are three separate internal
128-bit data buses, each connected to one of the memory blocks. Memory
blocks can store instructions and data interchangeably, with one access per
memory block per cycle. If the programmer ensures that program and data
are in different memory blocks, then data access can occur at the same
time as program fetch. Thus in one cycle, up to three 128-bit transfers can
occur within the core (two data transfers, and one program instruction
transfer).
The I/O Processor can use only one internal bus at a time, and the I/O
Processor competes with the core for use of the internal bus. Therefore in
one cycle, the processor can fetch four 32-bit instructions, and load or
store 256 bits of data (four 64-bit words or eight 32-bit words or sixteen
16-bit words or thirty-two 8-bit words).
ADSP-TS101 TigerSHARC Processor
Hardware Reference
2-1