Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 287

Table 7-5. Dual TCB Channel – Internal Memory TCB
Receiver TCB Configuration
Register Field
DI
DX
DY
DP TY
DP PR
DP 2DDMA
DP LEN
DP INT
DP DRQ
DP CHEN
DP CHTG
DP CHPT
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Description
Internal memory address
Number of words to transfer and address modifier. The
refers to X dimension data when the
Number of Y dimension words to transfer and address modifier when
the bit is set in the
2DDMA
Internal memory
Channel priority
1 – Increases the channel priority – internal bus DMA request
priority is high.
Sets the two-dimensional DMA mode
1 – Enables the two-dimensional DMA mode; the
becomes relevant (See"Two-Dimensional DMA" on page 7-45).
Must be the same as the value specified in the
ter's register.
TCB DP
Sets interrupt
1 – Interrupts the core once the complete block is transferred. (Enabled
if set in either the source or destination
Sets transfer mode
1 – Transfers each data item per
either the source or destination
Sets chaining mode;
1 – Enables chaining
This setting must be identical to transmitter
Defines register to be loaded; must be the same channel.
TCB
Chaining pointer – relevant when chaining is enabled.
Direct Memory Access
bit is set in the
2DDMA
register; otherwise irrelevant.
DP
LEN
register.)
TCBxDP
assertion. (Enabled if set in
DMARx
register.)
TCBxDP
.
TCB
register also
DX
register.
DP
register
DY
field of the transmit-
7-53