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47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 7-12. DSTAT (Bits 47-32) Register Bit Descriptions
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits17-15 continued on Figure 7-11
Figure 7-13. DSTAT (Bits 15-0) Register Bit Descriptions
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Direct Memory Access
CH8
CH9
CH10
CH11
Reserved
CH0 DMA channel # status
000 – Channel disabled
001 – Block transfer in progress
010 – Block transfer completed
011 – Reserved
100 – Initialization of an active
active value. When this condition occurs
the status can only be cleared by reading
from the
register.
DSTATC
101 – Illegal configuration in
could be as a result of setting the incor-
rect type field for an AutoDMA channel.
Again reading from
status.
110 – Reserved
111 – Address error – broadcast read. This
occurs if a source TCB address field is in
the range 0x1C000000 - 0x1FFFFFFF
CH1
CH2
CH3
CH4
CH5
TCB
with an
TCB
. This
can clear this
DSTATC
7-25
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