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which instructions are executed in parallel in each cycle. The instructions
do not have to be aligned in memory so that program memory is not
wasted.
The 6M bit internal memory is divided into three 128-bit wide memory
blocks. Each of the three internal address/data bus pairs connect to one of
the three memory blocks. The three memory blocks can be used for triple
accesses every cycle where each memory block can access up to four, 32-bit
words in a cycle.
The external port cluster bus can be configured to be either 32 or 64 bits
wide. The high I/O bandwidth complements the high processing speeds of
the core. To facilitate the high clock rate, the TigerSHARC processor uses
a pipelined external bus with programmable pipeline depth for interpro-
cessor communications and for Synchronous DRAM (SDRAM).
The four link ports support point-to-point high bandwidth data transfers.
Link ports have hardware-supported two-way communication.
The processor operates with a two cycle arithmetic pipeline. The branch
pipeline is two to six cycles. A branch target buffer (BTB) is implemented
to reduce branch delay. The two identical computation units support
floating-point as well as fixed-point arithmetic.
During compute intensive operations, one or both integer ALUs compute
or generate addresses for fetching up to two quad operands from two
memory blocks, while the program sequencer simultaneously fetches the
next quad instruction from the third memory block. In parallel, the com-
putation units can operate on previously fetched operands while the
sequencer prepares for a branch.
While the core processor is doing the above, the DMA channels can be
replenishing the internal memories in the background with quad data
from either the external port or the link ports.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Introduction
1-7
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