Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 182

Multiprocessing
TS0 IS THE
MASTER
SCLK
BR0
BR1
BR2
CPA
DPA
HBR
Figure 5-21. External Bus Arbitration Sequence; Only One Active
Inactive
HBR
TigerSHARC processor to interrupt background transfers of a regular pri-
ority DMA channel belonging to a master TigerSHARC processor and
gain control of the external bus. The current master in this case terminates
its transaction and passes the bus mastership to the requesting Tiger-
SHARC processor by deasserting its
TigerSHARC processors with high priority DMA transactions can request
the bus. The other requesting TigerSHARC processors deassert their
when they sense
cessor requests the bus by asserting their
TigerSHARC processor with the highest priority gains the bus mastership.
5-44
TURN
OVER
TS2 IS THE
CYCLE
MASTER
BY TIGERSHARC #2
is asserted. When more than one TigerSHARC pro-
DPA
T URN
OVER
TS0 IS THE
CYCLE
MASTER
. When is asserted, only
BR DPA
s along with
BR
ADSP-TS101 TigerSHARC Processor
Hardware Reference
TURN
OVER
TS1 I S THE
CYCLE
MASTER
;
DPA
s
BR
, the
DPA