Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 327

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-14. LSTATx (Lower) Register Bit Descriptions
Table 8-5. LSTATx Register Bit Descriptions
Bits
1–0
3–2
5–4
7–6
31–8
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Name Description
Receive Error
RER
00 – No error
01 – Verification byte error
10 – Receive time out
11 – Both errors
Receive Status
RST
00 – Receiver empty
01 – Receiver shift register partly full,
10 – Receiver
11 – Receiver full
Transmit Error
TER
00 – No error
01 – Connectivity error
10 – Transmit time out
11 – Both errors
Note any error causes hardware error interrupt. Reading
the Status register clears the error and resets the state
machine for a new transfer.
Transmit Status
TST
00 – Transmitter empty
01 – Transmitter partly full
11 – Transmitter full
Reserved
RER - Receive Error
RST - Receive Status
TER - Transmit Error
TST - Transmit Status
Reserved
buffer full, shift register empty
LBUFRx
Link Ports
buffer free
LBUFRx
8-25