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SDRAM Controller Commands
Refresh (REF) Command
The
command is a request to the SDRAM to perform a CBR (
REF
Before
) refresh transaction. This transaction is generated automati-
RAS
cally by the TigerSHARC processor and causes all addresses to be
produced internally in the SDRAM. Before executing the
the SDRAM controller executes a precharge (
bank. The next active (
a minimum delay equal to t
The refresh cycle is required by the SDRAM to keep the data valid. The
refresh frequency is set in the
ister (SDRCON)" on page 6-19). In a multiprocessing system, the refresh
is done by the current bus master. To eliminate problems caused by differ-
ences between TigerSHARC processors in refresh counter initialization,
every slave TigerSHARC processor monitors the external bus and resets its
own counter when identifying a refresh cycle.
Table 6-16. Pin State During REF Command
Pin
MSSD
CAS
RAS
SDWE
SDCKE
Self-Refresh (SREF) Command
The TigerSHARC processor enters self-refresh mode before the bus is
relinquished to the host. The purpose is to keep the SDRAM
self-refreshed in case the host doesn't interface with the SDRAM. If the
host can interface with the SDRAM, it releases the SDRAM from
6-42
) command is given by the controller only after
ACT
.
RC
register (see "SDRAM Control Reg-
SDRCON
State
low
low
low
high
high
ADSP-TS101 TigerSHARC Processor
command,
REF
) command to the active
PRE
Hardware Reference
CAS
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