Autodma0 Register; Autodma1Register - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Register Access Features
Table 2-16. AutoDMA Register
Register Quad AutoDMA Registers
AutoDMA register 0
AUTODMA0
AutoDMA register 1
AUTODMA1

AutoDMA0 Register

This is the AutoDMA channel 0 Data register. When writing to this regis-
ter, DMA channel 12 transfers the written data into the internal memory
address programmed in the DMA. This register cannot be read, and can
only be written through the multiprocessing address space. If the DMA is
not initialized, the data is lost.

AutoDMA1Register

This is the AutoDMA channel 1 Data register. When writing to this regis-
ter, DMA channel 13 transfers the written data into the internal memory
address programmed in the DMA. This register cannot be read, and can
only be written through the multiprocessing address space. If the DMA is
not initialized, the data is lost.
2-44
Direct Memory Address Remarks
0x180740 - 0x180743
0x180744 - 0x180747
ADSP-TS101 TigerSHARC Processor
Hardware Reference