Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 254

DMA Transfer Control Block Registers
Table 7-1. DPx Register Bit Descriptions
Bit Description
Chain Pointer
CHPT
Bits14–0 These bits contain Bits16–2 of the address in memory where the next
contents are to be found. Bits1–0 of the memory address are not required as the
address must be quad-word aligned. For example if the next
are stored at memory location
b00100001110001001010
Memory select for chain pointer
MS
Bits16–15 These bits specify the memory block in which the next
00 – Memory Block 0
01 – Memory Block 1
10 – Memory Block 2
11 – Reserved
Chaining destination channel
CHTG
1 This field specifies the DMA channel
Bits21–17
to by the
00000 – Channel 0 Source
00001 – Channel 0 Destination
00010 – Channel 1 Source
00011 – Channel 1 Destination
00100 – Channel 2 Source
00101 – Channel 2 Destination
00110 – Channel 3 Source
00111 – Channel 3 Destination
01000 – Channel 4 Link Port 0 Transmit
01001 – Channel 5 Link Port 1 Transmit
01010 – Channel 6 Link Port 2 Transmit
01011 – Channel 7 Link Port 3 Transmit
10000 – Channel 8 Link Port 0 Receive
10001 – Channel 9 Link Port 1 Receive
10010 – Channel 10 Link Port 2 Receive
10011 – Channel 11 Link Port 3 Receive
10110 – Channel 12 IFIFO AutoDMA0 Receive
10111 – Channel 13 IFIFO AutoDMA1 Receive
7-20
0x87128
(
0x21C4A
and fields should be loaded.
CHPT MS
TCB
TCB
TCB
TCB
TCB
TCB
TCB
TCB
ADSP-TS101 TigerSHARC Processor
TCB
- then the
0x8712B CHPT
).
contents can be found.
TCB
registers in which the quad-word pointed
TCB
TCB
TCB
TCB
TCB
TCB
TCB
TCB
TCB
TCB
TCB
Hardware Reference
register
TCB
register contents
field would contain