Table of Contents
Advertisement
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 2-7. WPxSTAT (Lower) Register Bit Descriptions
Cycle Counters – CCNT0 and CCNT1
The cycle counter is 64 bits long. The two Uregs that make up the cycle
counter are
CCNT0
two registers cannot be accessed with a long-word access; they can only be
accessed in two single accesses. These registers can be written in emulator
or supervisor modes only, although they are readable in all modes.
Trace Buffer – TRCB0 to TRCB7 and TRCBPTR
Each time the TigerSHARC processor executes a non-sequential fetch, the
PC of the non-sequentially fetched instruction is written into one of the
trace buffer registers. The first write is into trace buffer #0; the second to
#1, and so on in a circular manner. The trace buffer pointer (3 bits) iden-
tifies the last written trace buffer.
After reset, the trace buffer registers (
set to zero. All the trace buffer registers are read by software only.
For more information, see "Instruction Address Trace Buffer (TBUF)" on
page 9-9.
Watchpoint Address Pointers – WP0L, WP1L, WP2L, WP0H, WP1H
and WP2H
The watchpoint address pointers are 32-bit pointers defining the address,
or address range, of the watchpoints. Their value after reset is undefined.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
and
. When JTAG is reset,
CCNT1
Memory and Register Map
Value Watchpoint current counter value
CCNT
) and pointer (
TRCB
is cleared. These
) are all
TRCBPTR
2-29
Advertisement
Table of Contents
