Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 163

SCLK
ADDR
AA0 AA 1
DATA
RD
BRST
ACK
Figure 5-9. Burst Read Access Followed by Burst Read
extends the transaction pipeline for two cycles. The extended cycles begin
one cycle after the
extended for two additional cycles. All the slaves strobe address
the target slave of transaction samples datum,
signal is deasserted.
!
In Figure 5-10 on page 5-26, transaction
to different slaves. If a slave drives the
lowing transaction is to a different slave, the target slave of the
second transaction may not drive the
slave has completed the transaction. This applies to the cycle fol-
ADSP-TS101 TigerSHARC Processor
Hardware Reference
AA2 AA3 AB0
DA0
signal was deasserted—for example,
ACK
AB1 A B2
QUAD-WORD
DA1 DA2
, in the cycle that the
db0
and
ab0 ab1
signal low and the fol-
ACK
signal before the first
ACK
Cluster Bus
AB3
Q UAD-WORD
DA3 DB0 DB1
and are
ab2 db1
, and
ab1
ACK
are targeted
5-25