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7-37, 7-38, 7-51, 10-37
boot 10-32
chaining 1-22, 7-13, 7-15,
7-16, 7-18, 7-20, 7-21,
7-32, 7-33, 7-35, 7-38,
7-41–7-44, 7-46, 7-48,
7-49, 7-50, 7-52, 7-53,
7-54, 7-55, 7-56, 7-57,
7-58, 7-59, 7-60, 7-64,
7-65, 7-66
cluster bus transfers 7-7–7-8
control and status registers
7-23–7-31
DMA architecture 7-11–7-12
DMA channel 1-20, 1-22, 2-7,
2-43, 2-45, 3-6, 4-5,
4-6, 5-33, 7-7, 7-15–
7-23, 7-36–7-40, 7-66–
7-68, 8-5
DMA Control register DCNT
2-46, 7-26
DMA
Control
DCNTCL 2-46, 7-28
DMA
Control
DCNTST 2-46, 7-28
DMA Control register restric-
tions 7-28–7-31
DMA Control registers 7-26–
7-31
DMA controller 1-22, 7-7–
7-10, 7-32–7-49, 10-32
DMA interrupt 2-20–2-21, 4-2,
4-5–4-6, 7-48
DMA memory access 7-34–
ADSP-TS101 TigerSHARC Processor
Hardware Reference
register
register
DMA Architecture Overview 7-11
DMA Chaining 7-41
DMA Channel Control 7-15
7-36
DMA programming 7-14
DMA registers 2-41, 7-15–
7-31
DMA sequences 7-48–7-49
DMA Status register (DSTAT)
2-46, 7-23–7-25
DMA throughput 7-66–7-68
DMA
transfers
7-33–7-34
external port 2-43, 7-32, 7-50–
7-62
handshake mode 7-61
link input and IFIFO DMA
TCB 2-45
link output DMA TCB 2-45
link ports DMA 7-32, 7-63–
7-65, 8-5–8-7
link transfers 7-9
semaphores 7-59
TCB registers 7-15–7-23
Transfer Control Block (TCB)
registers 7-15
two-dimensional DMA 7-10,
7-17, 7-22, 7-28, 7-32,
7-36, 7-45–7-47, 7-51,
7-52, 7-53, 7-54, 7-55,
7-56, 7-57, 7-58, 7-59,
7-60, 7-64, 7-65, 7-66,
10-34, 10-35, 10-36,
10-37
INDEX
(overview)
v
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