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Figure 8-10 shows the effect of the delay between two TigerSHARC pro-
cessors. The transmitter (TigerSHARC processor A) sets
indicate a token switch enable. The receiver (TigerSHARC processor B)
senses this after a delay. The receiver then sets its
of the transmitter) low and waits to see if the transmitter regrets
LxCLKIN
the token switch. The token switch takes place if the transmitter has not
regretted the token switch. Refer to the data sheet for specific timing data.
Error Detection Mechanisms
The link ports support on-the-fly error checks. When the link detects an
error condition, it operates in the following sequence.
• The
TER
• If the
TTOE
Error check Enable), or
are set in the
"Hardware Error Operations" on page 4-8.)
• If the
VERE
registers, the
and a hardware error interrupt is set. (See "Hardware Error Opera-
tions" on page 4-8.)
• The link no longer continues to transmit/receive until the error sta-
tus is read (from the
After reading the status from the destructive address, it should be reinitial-
ized to start working.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
or
field in
RER
LSTATx
(Transmit Time Out check Enable),
RTOE
registers, a hardware error interrupt is set. (See
LCTLx
(checksum Verification Error Enable) is set in the
field in
RER
LSTATx
LSTATCx
LxCLKOUT
is set according to the error type.
(Receive Time Out check Enable) bits
is set according to this error type,
).
Link Ports
high to
LxCLKOUT
(which is
(Connectivity
CERE
LCTLx
8-17
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