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Memory Access Features
Broadcast Write
In Broadcast Write, a TigerSHARC processor or host writes the same data
to different TigerSHARC processors via multiprocessor memory space.
One TigerSHARC processor writes to the Broadcast memory space using
the external bus to distribute the same stream of data to all processors. A
common application would be when several processors perform different
algorithms on the same stream of data.
The number of source locations and destination registers listed in the
instruction determines whether broadcast or merged distribution is used.
Distribution is commonly used in a FIR filter application, where data is
loaded in quads then re-arranged into the groups needed. This requires a
Data Alignment Buffer, described in the next section.
Merged Distribution
In Merged Distribution, one instruction loads different data into two com-
pute blocks in the same TigerSHARC processor. Instruction syntax
determines how the data is distributed. For example, xyRq identifies two
quad-word Uregs, one in processing element X and one in processing ele-
ment Y. When the prefixes are absent the assembler assumes the order xy,
reverse the order of the processing elements by reversing the prefix (yx).
For long-word access, the processor distributes the MSW to processing
element X, and the LSW to element Y. For the quad-word access, two
MSWs are distributed to processing element X, and two LSWs are distrib-
uted to element Y.
Broadcast Distribution
In Broadcast Distribution, one instruction loads the same data into two
compute blocks in the same TigerSHARC processor. Broadcast distribu-
tion works with normal, long, or quad data accesses.
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ADSP-TS101 TigerSHARC Processor
Hardware Reference
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