Link Interrupts; Dma Interrupts - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Link Interrupts

The vector registers are:
•
IVLINK0
•
IVLINK1
•
IVLINK2
•
IVLINK3
After reset, the link interrupts are disabled and vectors are not initialized.
There are four link channels that normally work with their dedicated
DMA channels. While there is a data element in the receive buffer and its
DMA is not initialized, this link issues an interrupt.

DMA Interrupts

The vector registers are:
•
IVDMA0
•
IVDMA1
•
IVDMA2
•
IVDMA3
•
IVDMA4
•
IVDMA5
•
IVDMA6
•
IVDMA7
•
IVDMA8
ADSP-TS101 TigerSHARC Processor
Hardware Reference
– interrupt priority 6; level-triggered
– interrupt priority 7; level-triggered
– interrupt priority 8; level-triggered
– interrupt priority 9; level-triggered
– interrupt priority 14; edge-triggered
– interrupt priority 15; edge-triggered
– interrupt priority 16; edge-triggered
– interrupt priority 17; edge-triggered
– interrupt priority 22; edge-triggered
– interrupt priority 23; edge-triggered
– interrupt priority 24; edge-triggered
– interrupt priority 25 edge-triggered
– interrupt priority 29; edge-triggered
Interrupts
4-5