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SQCTL = xr0;;
rti(ABS);;
Clock Description and Jitter
The clock signal must be free of ringing and jitter. Clock jitter can easily
be introduced into a system where more than one clock frequency exists.
Clock Distribution
There must be low clock skew between DSPs in a multiprocessor cluster
and between DSPs and host or memory when communicating synchro-
nously on the external bus. The clock must be routed in a
controlled-impedance transmission line that can be properly terminated, if
necessary.
Figure 10-3 on page 10-16 illustrates the recommended clock distribution
using point-to-point connections with optional source termination (R
required for integrity). Source termination allows delays in each path to be
identical. Each device must be at the end of the transmission line because
it is only at that point that the signal has a single transition.
Other termination techniques are possible. It is recommended that design-
ers simulate for signal integrity. The traces must be matched length. Clock
signal traces should be in the PCB layer closest to the ground plane to
keep delays stable and crosstalk low. More than one device may be at the
end of the line, but the wire length between them must be short. The
ADSP-TS101 TigerSHARC Processor
Hardware Reference
/*Write back to Sequence Control Register*/
/*Return from interrupt serviceroutine*/
System Design
, if
T
10-15
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