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AutoDMA Register Control
The AutoDMA is a technique used to implement a slave mode DMA.
There are two virtual registers—
AutoDMAs has an AutoDMA channel associated with it, channels 12 and
13, respectively. When an external master (host or another TigerSHARC
processor) writes to one of the AutoDMA registers, this register issues a
DMA request to its associated channel and the DMA channel transfers the
data to internal memory according to its
64- or 128-bit internal data width can be used when transferring data
between the data registers and internal memory. The DMA data registers
channel is enabled as long as the
ter
. Control bits and chaining address are as defined in
DP
If chaining is enabled, one
"
If you write to AutoDMA while it is not initialized, the written
data is lost, and an error is indicated in the
the "SYSTAT/SYSTATCL Register" on page 2-31 for additional
information.
DMA Transfers
The following subsections discuss the operation of the TigerSHARC pro-
cessor's DMA controller and DMA transfers.
Internal Memory Buses
DMA controller operations are carried out on any one of the three inter-
nal memory buses. All I/O ports (link and external) are connected to the
internal memory via the three memory buses. For more information, see
"Processor Microarchitecture" on page 5-3. The DMA controller gener-
ates an internal memory access on one of these buses.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
and
AutoDMA0
TCB
field is not set to 000 in the
TY
register is loaded.
TCB
Direct Memory Access
. Each of the
AutoDMA1
programming. Either 32-,
register
TCB
register. Refer to
SYSTAT
regis-
TCB
.
DP
7-33
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