Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 200

SDRAM Physical Connection
• – Data Mask for High Word (data Bits63–2
HDQM
• – Clock Enable
SDCKE
In large memory systems, there are often many SDRAM chips that can
overload the address bus. The scheme for a 32-bit connection is as follows.
• SDRAM address Bits9–0 are connected to TigerSHARC processor
ADDR25–16
• SDRAM address Bits15–0 are duplicated on TigerSHARC proces-
sor
ADDR31–16
• SDRAM address Bit10 is connected to TigerSHARC processor pin
SDA10
• SDRAM address Bits15–11 are connected to TigerSHARC proces-
sor
ADDR31–27
The scheme for a 64-bit bus is as follows.
• SDRAM address Bits9–0 are connected to TigerSHARC processor
ADDR26–17
• SDRAM address Bit10 is connected to TigerSHARC processor pin
SDA10
• SDRAM address Bits14–11 are connected to TigerSHARC proces-
sor
ADDR31–28
Another option to reduce the load is to buffer the address and control sig-
nals in registers to delay these signals in a cycle. In this case the pipeline
depth bit in
SDRCON
6-10
(or as many as required)
(or as many as required)
should be set.
ADSP-TS101 TigerSHARC Processor
Hardware Reference