Reset And Boot - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Reset and Boot

The TigerSHARC processor has three levels of reset:
• Power-up reset – After power up of the system, and after strap
options are stable, the
serted (high) according to the specifications detailed in the
ADSP-TS101 TigerSHARC Embedded Processor Data Sheet. During
power up,
the JTAG Test Access Port (TAP). For additional details, refer to
Analog Devices Engineer- to-Engineer Note EE-68 "Analog Devices
JTAG Emulation Technical Reference (2.4)", available on the Analog
Devices Internet site: http://www.analog.com.
• Normal reset – For any resets following the power up reset
sequence, the
tions detailed in the ADSP-TS101 TigerSHARC Embedded
Processor Data Sheet.
• Core reset (software reset) – When setting the
the core is reset, but not the external port or I/O. (See "Sequencer
Control Register – SQCTL" on page 2-16.) After a core reset, boot
does not start automatically.
Hardware reset is performed by asserting the
reset (for hardware reset only, not core reset), all TigerSHARC
processor output pins are three-stated. The strap pins are sampled
during this period. The
that require cycle-by-cycle predictive behavior, the
asserted according to AC specifications. In this case, an integer
value (2, 3, 4, 5, or 6) should be used for
source should be used for
ADSP-TS101 TigerSHARC Embedded Processor Data Sheet for the
AC specifications.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
RESET
must also be asserted (low) to ensure proper reset of
TRST
pin must be asserted according to the specifica-
RESET
RESET
LCLK
pin must be asserted (low) and deas-
SWRST
RESET
pin is asynchronous. For systems
LCLKRAT
and pins. Refer to the
SCLK
System Design
bit in ,
SQCTL
pin. During
should be
RESET
, and the same
10-17