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TigerSHARC Pipelined Interface
An IDLE cycle is inserted between transactions to prevent contention
between drivers. Figure 5-7 on page 5-21 shows two quad-word read
transactions where each transaction takes four bus cycles. The two transac-
tions are separated by an IDLE cycle. IDLE cycles are inserted in the
following cases.
• Read followed by read from two different zones, different Tiger-
SHARC processors, host or combination of the above, if the
second read's pipeline depth is smaller or equal to the first read
pipeline depth.
• Read followed by read from the same zone, and the IDLE bit of
this zone in the
• Read followed by write or write followed by read, if the second
transaction's pipeline depth is smaller or equal to the first transac-
tion pipeline depth.
If the corresponding IDLE bit is cleared, sequences of write, a sequence of
a multicycle transaction, or sequences of reads from the same slave are not
separated with an IDLE cycle.
Sequential accesses with different pipeline depths receive special treat-
ment. If the first transaction has a smaller pipeline depth than the second
transaction, the address cycles are issued with no gap, even though there
may be a gap between the data cycles. If the pipeline depth of the first
transaction is larger than the pipeline depth of the second, the transactions
cannot be sequential. As shown in Figure 5-8 on page 5-23, the second
transaction address cycle is delayed after the first transaction. The purpose
of the delay is to keep the data cycles of the two transactions separate. The
delay between the two transactions is the difference in the pipeline depth
if no IDLE cycle is inserted, or the difference between the pipeline depths
plus one if the conditions for IDLE are true. If the difference between the
pipeline depths is one, an IDLE cycle is inserted. The second transaction
address cycle begins two cycles after the end of the first transaction.
5-22
register is set.
SYSCON
ADSP-TS101 TigerSHARC Processor
Hardware Reference
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