Table 6-2. Word Page Size 256, 64-Bit Bus Width
Physical
TigerSHARC
Processor Pin
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
SDA10
A11
A12
A13
A14
A15
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Bank Active Cycle
Column Access Cycle
Internal Address
Internal Address
8
0
9
1
10
2
11
3
12
4
13
5
14
6
15
7
16
8
17
9
18
10
19
Zero
Irrelevant
Irrelevant
20
20
21
21
22
22
23
23
SDRAM Interface
Physical SDRAM Pin
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
NC
A11 or Bank
A12 or Bank
A13 or Bank
A14 or Bank
6-13
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