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A generic slave device (i.e., a device other than a TigerSHARC acting as
slave) can use the
and then automatically increment that address as successive data words
arrive.
The
signal must be connected in a multiprocessor TigerSHARC sys-
BRST
tem in order to qualify long-word and quad-word accesses between DSPs.
The
signal may optionally be connected between a host device and a
BRST
TigerSHARC. If burst accesses (including but not limited to long-word
and/or quad-word accesses) between host and TigerSHARC processor are
required, then BRST must be connected and used to qualify these accesses
for the TigerSHARC slave.
Figure 5-6 on page 5-20 and Figure 5-7 on page 5-21 illustrate examples
of different types of sequential transactions in a 32-bit bus. Figure 5-6 on
page 5-20 shows a quad-word write that is executed in four cycles, where
the
pin is asserted on the first three cycles. This transaction is fol-
BRST
lowed by a word write, and then two long writes where the
in the first cycle of each transaction. The pipeline depth is one cycle since
these are write transactions.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
signal to accept the first address in a burst transfer
BRST
Cluster Bus
is asserted
BRST
5-19
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