Understanding Dqm Operation - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

In multiprocessors systems, where the bus mastership changes, the current
bus master automatically issues a precharge command (
is relinquished to the new bus master. This way, the new bus master can
safely start accessing the SDRAM by simply issuing an activation com-
mand ( ).
ACT
In TigerSHARC multiprocessor systems where SDRAM is used, the Mode
Register Set sequence is only issued by the TigerSHARC processor with
= . Therefore, a TigerSHARC processor with
000
in every multiprocessor system.

Understanding DQM Operation

The /
HDQM LDQM
three-states the SDRAM DQ buffers when performing 32-bit writes
HDQM
to even addresses in a 64-bit bus configuration, or when bus is configured
as a 32-bit bus.
ing writes to odd addresses in a 64-bit bus configuration. This data mask
function does not apply for read operations, where the
are always low (inactive).
Powering Up After Reset
After reset, once the
code, the controller initiates the selected power up sequence. The exact
sequence is determined by the Init Sequence bit in the
a multiprocessing environment, the power up sequence is initiated by the
TigerSHARC processor with
reset the controller and does not re-initiate a power up sequence.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
pins are used by the controller to mask write operations.
three-states the SDRAM DQ buffers when perform-
LDQM
register is written to in the user application
SDRCON
=
ID
=
ID
. Note that software reset does not
000
SDRAM Interface
) before the bus
PRE
ID
must be present
000
and pins
LDQM HDQM
register. In
SDRCON
6-29