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Table 9-1. Debug Concepts
Debug Tools
Watchpoints
Multiprocessing
Capability
Trace History
Cycle Count
Performance
Monitoring
Access to Protected Registers Provides access to protected registers. Protected registers are only
Watchpoint Counters
Exception
Watchpoints
Address watchpoints allow the user to examine the state of the processor
whenever a set of user-defined memory access conditions occurs.
There are three watchpoint sets that can operate in parallel. At each
watchpoint, the user can define conditions for bus access cycles and the
operation the TigerSHARC processor should execute when these occur.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Debug Feature
Allows a user to specify particular watchpoint address ranges and
conditions that halt the processor when those conditions are met.
The user can then examine the state of the processor, restore that
state, and continue instruction execution. Software breakpoints
and single step are implemented using watchpoint as well.
Allows a user to single step and set breakpoints in a multiproces-
sor system.
Allows a trace of the program counter to be recreated. An on-chip
trace buffer (FIFO) stores the last eight branches (all discontinu-
ous values of the program counter) taken by the program
sequencer, allowing the recent program path to be recreated.
Provides the basic functionality for all code profiling functions.
Allows internal resources to be monitored unobtrusively. The
debugger can specify which internal resource(s) should be
monitored.
accessible in supervisor mode or ICE. They cannot be accessed by
user mode and are protected from accidental modifications that
could cause system damage.
Allows the user to search for the nth occurrence of an event before
halting.
Aborts execution of the next and the following piped instructions.
For more information, see "Exceptions" on page 4-23.
Debug Functionality
9-3
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