Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 137

The exceptions are treated differently from other interrupts:
• The exception is tied to the instruction that caused it. The excep-
tion process begins when the instruction that caused the exception
reaches pipeline stage EX2. When this occurs, all instructions in
the pipeline are aborted. If the instruction that caused the excep-
tion was speculative and it was aborted, the exception does not take
place. Unlike an abort, a predicated instruction that is not executed
due to the condition can still cause the exception.
• The return address is saved in a different register to enable nesting
between the hardware interrupt and the exception. The registers
are
RETS
• If the exception is disabled when it is occurring, it is not latched. It
is not latched because it is irrelevant to do so without the return
address pointing to the cause (
the exception is lost.
• When an exception occurs, Bit60 of
exception routine does not clear the
There are two reasons for this. First, an exception may occur
while
change due to the exception handling. Secondly, the pur-
pose of protecting the
irrelevant because all hardware interrupts have a lower pri-
ority than (software) exceptions. Thus, there is no need to
protect the
• In order to protect the old
execute the following instruction lines, then jump to
[j31+temporary address] = RETI;;
RETI = RETS;;
RTI; RETI = [j31+temporary address];;
ADSP-TS101 TigerSHARC Processor
Hardware Reference
for exception or
DBGE
is set and the value of
PMASK60
register before returning (by using
RTI
for emulation trap.
or registers). In these cases
RETS DBGS
is not set.
PMASK
.
PMASK60
PMASK60
register from another interrupt is
RTI
value before returning you must
RETI
Interrupts
from an
RTI
may not
).
RETIB
:
RETS
4-25