Dma Channels - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Controller Operations

DMA Channels

Memory-to-memory DMA channels consist of two
receive and one for transmit) that specify:
• A data buffer in internal and external memory
• Control fields
• The method of requesting a transfer
Link memory DMA channels consist of one
a data buffer in internal or external memory, control fields, and the hard-
ware required to request DMA service. Any receiver link channel
register can define another link port as a memory-mapped device.
AutoDMA register memory is similar to link memory except that
AutoDMA registers are always receivers. The AutoDMA register memory
cannot define another link port as a memory-mapped device. The des-
TCB
tination must always be to internal memory.
The DMA controller contains priority logic to determine which channel
or I/O can drive which bus in any given cycle.
DMA Memory Accesses
The DMA is able to access the full address space. Each channel includes
an Index register (
which are used to set up a data buffer in the memory.
The 32-bit
TCB
initialized with a starting address for the data buffer. The address in the
register is directed to one of the internal memories, to a link register
address, or to the external memory space. This must be consistent with the
transfer type—
TCB
page 7-18.)
7-34
) and a Modify register (
DIx
register holds the block's initial address and must be
DI
field in
TY DPx
TCB
register that also specifies
TCB
) in its
DMx
register. (See "DPx Register" on
ADSP-TS101 TigerSHARC Processor
registers (one for
TCB
register,
TCB
DI
Hardware Reference