Status Register (Lstatx) - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Table 8-4. LCTLx Register Bit Descriptions (Cont'd)
Bits Name Description
11 Receive Time Out check Enable
RTOE
Enables hardware error interrupt on time out check for received data.
When set, a hardware error interrupt is issued.
Upon reset this bit is cleared.
31–12 Reserved
1 Both transmitter and receiver have to work at the same clock speed, although the clock doesn't
need to be fully synchronous.
2 Refer to the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet for timing specifications
and frequency limitations.
After reset:
• The register is initialized to 0x400—receive enable.
• Transmit is disabled; packet size is 64 quad-words.
• Clock division is by 8.
• pin is disabled.
DIR
• Verification is disabled and all error checks are disabled.
In normal operation, the programmer configures all Link Control register
features just once after reset.

Status Register (LSTATx)

The Status register holds error and status information for every link port.
There are four status registers, one for each link port. The status registers
are read-only—note however, that a read from a clear address clears the
error fields
RER
ADSP-TS101 TigerSHARC Processor
Hardware Reference
and .
TER
Link Ports
8-23