Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual page 404

INDEX
3-3, 5-9, 8-2
VIRPT (Vector Interrupt regis-
ter) 4-7
watchpoint control
(WPiCTL) 2-25, 9-4–
9-7
watchpoint status
(WPiSTAT) 2-27, 9-8
Register Access Features 2-9
register groups 2-9–2-47
Branch Target Buffer registers
2-10
bus control/status
2-10, 2-30, 2-44
compute block register files
2-10
debug logic registers 2-10,
2-21
DMA registers 2-10, 2-41
external port registers 2-10,
2-47
IALU registers 2-10, 2-14–
2-15, 4-19
interrupt and sequencer regis-
ters 2-20
interrupt registers 2-10, 4-1
interrupt vector register groups
2-20
link registers 2-10, 2-47
sequencer registers 2-10
Register J31
JSTAT 2-15
Register K31
xvi
Register Space 2-9
registers
register
related documents -xxiv
register relative addresses 1-15
Relative Addresses for Relocation
1-15
relative addresses for relocation
1-15
Reset 10-11
registers reset 3-4, 3-10, 4-2, 4-4, 4-5, 4-6,
4-7, 4-8, 4-9, 4-10, 5-15, 5-40,
10-11, 10-17
RESET (Reset) 3-4, 10-17
Reset and Boot 8-7, 10-17
Resources and References 10-38
Resuming a DMA Sequence 7-49
RETI register (Return from Inter-
rupt) 4-13, 4-15, 4-16, 4-18, 9-2
Return from Interrupt see RTI in-
struction (Return from Interrupt)
Return to Normal Operation 3-8
Returning From Interrupt 4-22
Rotating Priority 7-39
Row Address Strobe (RAS) 5-1,
6-7, 6-9
RTI instruction (Return from Inter-
rupt) 4-13, 4-15, 4-19, 4-22–4-23,
4-24, 4-25
ADSP-TS101 TigerSHARC Processor
KSTAT 2-15
files 1-9
saving and restoring 1-15
core reset 10-17
JTAG reset 9-13
Hardware Reference