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Operation Modes
In emulation mode, the program access to the debug registers (groups
0x1B and 0x3D) may be executed only using the instruction:
UREG = UREG;
The
, cycle count, performance monitors, and trace buffer are inactive
BTB
in emulation mode. Except for
tions (
,
jump
call
cannot be used in emulation mode. The Run Test /Idle (RT/I) register can
only be used without condition.
If the external reset pin is being asserted, and an external emulation excep-
tion is generated, the TigerSHARC processor core exits reset internally,
enters emulation mode, and waits to fetch the value of
loaded from the JTAG.
In emulation mode, only the core works. The external interfaces (BIU,
DMA and links) are still held in reset, although their internal registers can
be accessed by the instructions inserted via JTAG and
enables an EZ-ICE to initialize the TigerSHARC processor internal regis-
ters and memory while it is still in reset and start its run from a known
state.
Supervisor Mode
Most code that is not intended to run under an operating system should
be designed to run in supervisor mode. Supervisor mode allows the pro-
gram to access all resources. The TigerSHARC processor is in supervisor
mode when one of these two conditions is true:
• The
NMOD
Control Register – SQCTL" on page 2-16.
• An interrupt routine is executed—indicated by non-zero
For more information, see "PMASK Register" on page 4-13.)
3-4
if true
,
,
RDS
conditional
bit in
is set. For more information, see "Sequencer
SQCTL
—
(np), all control flow instruc-
RTI
, and so on.) and the
ADSP-TS101 TigerSHARC Processor
instruction
IDLE
, which is
EMUIR
. This feature
EMUIR
.
PMASK
Hardware Reference
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