Optimizing The Clock Common-Mode Voltage; Analog Control Registers; Mirror Roll-Off Frequency Control; Voltage Reference - Analog Devices AD9739 Manual

MaxSkew + Jitter = 800 ps – 344 ps – 100 ps
MaxSkew + Jitter = 456 ps
OPTIMIZING THE CLOCK COMMON-MODE
VOLTAGE
To optimize the interface and handoff timing, there is an
additional system that sets the common-mode voltage of the
clock, which can be used to properly align the crossing point of
the DACCLK_P and DACCLK_N signals to ensure that the
duty cycle of the clock is set properly. Figure 99 shows how the
common-mode voltage of DACCLK_P and DACCLK_N is set.
Eight switches controlled by the SPI bits, CLKP_OFFSET[3:0]
(Register 0x22, Bits[3:0]) and CLKN_OFFSET[3:0] (Register
0x23, Bits[3:0]), for both the DACCLK_P and DACCLK_N
signals.
The DIR_P (Register 0x22, Bit 4) and DIR_N (Register 0x23,
Bit 4) bits determine the direction of the adjustment. If
DIR_P/DIR_N is low, the common-mode voltage decreases
with the CLKP_OFFSET/CLKN_OFFSET values. If DIR_P/
DIR_N is high, the common-mode voltage increases with the
CLKP_OFFSET/CLKN_OFFSET values, as shown in Figure 100.
When both CLKP_OFFSET and CLKN_OFFSET bits are set to
zero, the feedback path forces the common-mode voltage to be
set to approximately 0.9 V. The optimal ac performance occurs
at a setting of −15 on both the CLKP and CLKN offset bits.
CLKx_OFFSET
DIR_x = 0
DACCLK_x
CLKx_OFFSET
DIR_x = 1
CLKVDD
Figure 99. Clock Common-Mode Control
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
–15 –13 –11 –9 –7 –5 –3 –1
OFFSET CODE
Figure 100. Common-Mode Voltage with Respect to
CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N
CLKP
CLKN
1 3 5 7 9 11 13 15
Rev. A | Page 47 of 56

ANALOG CONTROL REGISTERS

The AD9739 includes some registers for optimizing its analog
performance. These registers include noise reduction in the
output current mirror and output current mirror headroom
adjustments.

MIRROR ROLL-OFF FREQUENCY CONTROL

Using MSEL[1:0] (Register 0x33, Bits[1:0]), the user can adjust
the noise contribution of the internal current mirror to
optimize the 1/f noise. Figure 101 shows the MSEL bits vs. the
1/f noise with 20 mA full-scale current into a 50 Ω resistor.
–110
–115
–120
–125
–130
–135
–140
1
FREQUENCY (kHz)
Figure 101. 1/f Noise with Respect to the MSEL Bits

VOLTAGE REFERENCE

The AD9739 output current is set by a combination of
digital control bits and the I120 reference current, as shown
in Figure 102.
AD9739
V
BG
1.2V
VREF
–
I120
+
1nF
10kΩ
I120
AVSS
Figure 102. Voltage Reference Circuit
The reference current is obtained by forcing the band gap
voltage across an external 10 kΩ resistor from I120 (Pin B14) to
ground. The 1.2 V nominal band gap voltage (VREF) generates
a 120 μA reference current in the 10 kΩ resistor. This current is
adjusted digitally by FSC[9:0] (Register 0x06 and Register 0x07)
to set the output full-scale current I
IOUTFS = 0.0226 × FSC[9:0] + 8.5845
The full-scale output current range is approximately 8 mA to
31 mA for register values from 0x000 to 0x3FF. The default
value of 0x200 generates 20 mA full scale. The typical range is
shown in Figure 103.
AD9739
10 100
FSC[9:0]
DAC
CURRENT
SCALING
IFULL-SCALE
.
FS