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External Port
External Bus and Host Interface
The TigerSHARC processor external port (EP) provides an interface
between the core processor and the 32/64-bit parallel external bus. The
external port contains FIFOs that maintain the throughput of an external
bus that is shared with multiple processors and peripherals—each of which
may operate at speeds other than that of the core.
The most effective way to access external data in the TigerSHARC proces-
sor is through the DMA. This runs in the background, allowing the core
to continue processing while new data is read in or processed data is writ-
ten out. Multiple DMA data streams can occur simultaneously, and the
use of FIFOs helps to maintain throughput in the system.
Burst accesses are provided through the
device on the bus to accept the first address and then automatically incre-
ment that address as successive data words arrive.
External Memory
The TigerSHARC processor external port provides the processor interface
to off-chip memory and peripherals. The off-chip memory and peripherals
are included in the TigerSHARC processor unified address space. The
separate on-chip buses are multiplexed at the external port to create an
external system bus with a single 32-bit address bus and a single 64-bit
data bus. External memory and devices can be either 32 or 64 bits wide.
The TigerSHARC processor automatically packs external data into either
32-, 64-, or 128-bit word widths, the latter being more efficient for reduc-
ing memory access conflicts.
On-chip decoding of high order address lines (to generate memory block
select signals) facilitates addressing of external memory devices. Separate
control lines are also generated for simplified addressing of page mode
DRAM.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
pin, which allows a slave
BRST
Introduction
1-19
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