Table of Contents
Advertisement
Slow Device Protocol
The TigerSHARC processor supports a slow device protocol that can be
used for simple devices. The slow device protocol can be configured for
address spaces belonging to bank0, bank1, or host. The slow device proto-
col is set by programming the relevant bits in the
• Slow = 1
• Pipeline depth = 0b00 (fixed when slow bit is set)
• Wait cycles = programmed according to system requirements
• IDLE cycle = 1 (fixed when slow bit is set)
The purpose of this setup is to enable a direct connection to simple and
low-performance, non-critical memories or peripherals. The protocol can
work with synchronous or asynchronous devices.
The basic protocol, when the configuration is "zero wait cycles", is shown
in Figure 5-11 on page 5-28 and Figure 5-12 on page 5-29. The memory
select is asserted to begin the transaction and the address is driven with it.
In the next cycle, the
asserted. Data is driven by the TigerSHARC processor if the transaction is
write. If the transaction is read, the slave can start driving the data. The
TigerSHARC processor latches the data at the end of this cycle. For the
zero-wait-cycles configuration, wait cycles cannot be inserted by deassert-
ing the
signal.
ACK
In the slow protocol, the
select signals. The external memory device used with this protocol should
be able to latch the data on the first rising edge of either
ADSP-TS101 TigerSHARC Processor
Hardware Reference
or
signal (according to the transaction type) is
RD
WRx
signals act as control signals and not as
MS0-1
Cluster Bus
register.
SYSCON
or the
MS0-1
WR
5-27
Advertisement
Table of Contents
