Dma Control And Status Register - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Register Access Features
Table 2-18. Link Port Receive DMA Register (Cont'd)
Register Link Input and IFIFO DMA TCBs
Quad (DMA channels 8, 9, 10, 11, 12, 13)
DMA channel 11
DC11
Reserved
DMA channel 12
DC12
DMA channel 13
DC13
1 DMA registers can be accessed only as quad-words.

DMA Control and Status Register

The Status register
ing the Status register from the clear bits address
in it are cleared, and changed to IDLE state
Table 2-19. DMA Control and Status Register
Register Quad DMA Control)
DMA control register
DCNT
DMA control register set bits
DCNTST
DMA control register clear bits
DCNTCL
DMA status register
DSTAT
DMA status register clear bits
DSTATC
2-46
TCB
TCB
TCB
is read only, and has two addresses. When read-
DSTAT
ADSP-TS101 TigerSHARC Processor
Direct Memory Address
0x18044C
0x18044D
0x18044E
0x18044F
0x180450 - 3
0x180458
0x180459
0x18045A
0x18045B
0x18045C
0x18045D
0x18045E
0x18045F
, all the error codes
DSTAT
.
DSTATC
Direct Memory Address Reset
0x180460
0x180464
0x180468
0x18046C - F
0x180470 - 3
Hardware Reference
1
Reset Value
0x5780 0000
0x0000 0000
0x0100 0004
0x0000 0000
0x5780 0000
0x0000 0000
0x0100 0004
0x0000 0000
0x5780 0000
0x0000 0000
0x0100 0004
0x0000 0000
value
1
0x0
1
1
2
Read only
2
Read only