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DMA Transfer Control Block Registers
DPx Register
This register is split into two fields, where the first is dedicated to DMA
control and the second is dedicated to chaining.
TY Specifies the device type
2DDMA Two-dimensional DMA
DRQ DMA request enable
CHEN Chaining enabled
CHTG Chaining destination channel
Figure 7-8. DPx (Upper) Register Bit Descriptions
7-18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PR Determines priority
LEN Operand length
INT Interrupt enable
0
0
0
0
0
0
0
MS Bit 15 continued on Figure 7-9
ADSP-TS101 TigerSHARC Processor
0
0
0
0
0
0
0
Hardware Reference
0
0
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