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Processor Microarchitecture
Arbitration is performed on each internal bus separately, including the vir-
tual bus. The priority on the internal bus is:
• High priority IFIFO transactions
• High priority DMA transactions
• Load, Store, and other data transfer instructions
• Low priority IFIFO transactions
• Low priority DMA transactions
• Instruction fetch
The DMA request priority is determined by the source
(see "DPx Register" on page 7-18).
The IFIFO request priority is high in the following cases.
• Direct read by an external master
• Broadcast write transaction in the IFIFO
• Write to internal address (the result of a DMA transaction) and the
destination
• IFIFO is full (three or more transactions in the IFIFO). The
request priority is high in order to prevent delays on the external
bus.
In all other cases, the IFIFO request has low priority.
5-10
priority bit is set
TCB
ADSP-TS101 TigerSHARC Processor
priority bit
TCB
Hardware Reference
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