Sdram I/O Pins - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

SDRAM I/O Pins

Table 6-1 lists the I/O pins associated with the SDRAM. Other bus inter-
face I/O pins are detailed in Table 5-1 on page 5-4.
Table 6-1. SDRAM I/O Pins
Signal Description
Address Bus
ADDR31-0
The TigerSHARC processor issues addresses for accessing memory and peripherals
on these pins. In a multiprocessor system, the bus master drives addresses for
accessing internal memory or I/O processor registers of other ADSP-TS101S
DSPs. The TigerSHARC processor inputs addresses when a host or another Tiger-
SHARC processor accesses it's internal memory or I/O processor registers.
External Data Bus
DATA63-0
Data and instructions are received and driven by the TigerSHARC processor, on
these pins.
Memory Select SDRAM
MSSD
MSSD
space.
SHARC processor issues an SDRAM command cycle access to
0b000001
processor.
Row Address Strobe
RAS
When sampled low,
SDRAM. In other SDRAM accesses,
according to SDRAM specification.
Column Address Strobe
CAS
When sampled low,
of SDRAM. In other SDRAM accesses,
cute according to the SDRAM specification.
Low Word SDRAM Data Mask
LDQM
When
DQ buffers.
inactive on read transactions. On write transactions,
an odd address word on a 64-bit memory bus to disable the write of the low word.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
is asserted whenever the TigerSHARC processor accesses SDRAM memory
is a decoded memory address pin that is asserted whenever the Tiger-
MSSD
). in a multiprocessor system is driven by the master TigerSHARC
MSSD
indicates that a row address is valid in a read or write of
RAS
indicates that a column address is valid in a read or write
CAS
is sampled high, the TigerSHARC processor three-states the SDRAM
LDQM
is valid on SDRAM transactions when
LDQM
SDRAM Interface
defines the type of operation to execute
RAS
defines the type of operation to exe-
CAS
CAS
is active when accessing
LDQM
(=
ADDR31–26
is asserted and is
6-7